3#include <cuda_runtime.h>
6#include <cuda/std/concepts>
23#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000
31template <
typename QueryScore,
typename ReferenceScore>
32__host__ __device__
inline bool
35 return (
reinterpret_cast<uintptr_t
>(
query) & mask) == 0U &&
36 (
reinterpret_cast<uintptr_t
>(reference) & mask) == 0U;
48 static_assert(
sizeof(T) == 4 ||
sizeof(T) == 8,
"T must be uint32_t or uint64_t");
50#if __CUDA_ARCH__ >= 1000
51 if constexpr (
sizeof(T) == 8) {
52 asm volatile(
"ld.global.nc.v4.u64 {%0, %1, %2, %3}, [%4];"
53 :
"=l"(out[0]),
"=l"(out[1]),
"=l"(out[2]),
"=l"(out[3])
56 asm volatile(
"ld.global.nc.v8.u32 {%0, %1, %2, %3, %4, %5, %6, %7}, [%8];"
68 if constexpr (
sizeof(T) == 8) {
69 asm volatile(
"ld.global.nc.v2.u64 {%0, %1}, [%2];" :
"=l"(out[0]),
"=l"(out[1]) :
"l"(ptr));
70 asm volatile(
"ld.global.nc.v2.u64 {%0, %1}, [%2];"
71 :
"=l"(out[2]),
"=l"(out[3])
74 asm volatile(
"ld.global.nc.v4.u32 {%0, %1, %2, %3}, [%4];"
75 :
"=r"(out[0]),
"=r"(out[1]),
"=r"(out[2]),
"=r"(out[3])
77 asm volatile(
"ld.global.nc.v4.u32 {%0, %1, %2, %3}, [%4];"
78 :
"=r"(out[4]),
"=r"(out[5]),
"=r"(out[6]),
"=r"(out[7])
__host__ __device__ bool wide_rows_aligned(QueryScore const *query, ReferenceScore const *reference) noexcept
True when both row bases meet load_256_alignment on the compiled architecture.
__device__ __forceinline__ void load_256_global_nc(const T *ptr, T *out)
Loads 256 bits from global memory using the non-coherent cache path.
__host__ __device__ constexpr uint32_t load_256_alignment() noexcept
Byte alignment load_256_global_nc requires on the compiled architecture.